`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/24 10:43:24
// Design Name: 
// Module Name: reg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module register(
    input clk,
    input data_in_en,
    input data_out_en,
    inout [15:0] data_bus,
    input rst_n
    );
    reg [15:0] data_reg;
    always @(posedge clk ) begin
        if (rst_n == 1'b0) begin
            data_reg <= 16'h0000;
        end
        else if (data_in_en) begin
            data_reg <= data_bus;
        end
    end
    assign data_bus = data_out_en ? data_reg : 16'hzzzz;
endmodule
